Compiled from outside sources; Adam Connors, DigiTimes.com [Monday 8 April 2002]
The process for sub-0.10-micron thin-film, low-resistance (k) material production, stalled under the burden of bad market conditions and slow manufacturing technology advancement, is beginning to achieve acceptance due to a group of key decisions and announcements this past week.
US-based research firm Kline & Co. recently released a study detailing the slow advance of low-k dielectrics, used in advanced interconnect structures on ICs, but went on to say that even though the movement is slow, it is due to produce great advances in the industry.
Currently, chip companies have had to work around resistance-capacitance (RC) delay problems by aligning circuits in unwieldy ways, problems that low-k materials could alleviate. Dow Chemical, heavily backed by IBM Microelectronics Division, hopes that the new cooperative announced last week between IBM, Sony, Sony Computer Entertainment (SCE) and Toshiba will push low-k material development known as its SiLK technology further into the mainstream. The R&D partnership is aimed at moving silicon-on-insulator (SOI) and other advanced semiconductor process technologies into cost-sensitive consumer electronics ICs, said Mark LaPedus of Silicon Strategies.
While the IBM and Japanese co-op is currently the biggest backer of the movement, another US company, Dielectric Systems, announced on April 5 that it has met some advanced benchmarks in low-k production and plans a manufacturing plant in Hsinchu, Taiwan. A 12-inch wafer beta tool for processing copper-based chips at 0.09 and 0.065-microns is planned for offer this month by the firm, pushing k values to 2.0 and below.
According to Silicon Strategies, the first tool is set to be shipped to “an undisclosed semiconductor consortium in Japan … a key microprocessor manufacturer as well as large logic chip maker in the U.S. and Japan.”
Related story:
TSMC sees copper interconnect as next mainstream technology (Sep 8, 2000)
