Compiled from outside sources; Adam Connors, DigiTimes.com [Thursday 11 April 2002]
A wide range of rapid-fire initiatives has already emerged from the beginning of a TSMC roadshow throughout the US, which began in San Jose this week and moves into the next, as the world’s largest foundry unveils some both unexpected and highly progressive directives.
In its grandest statement, TSMC vice president of corporate marketing Genda Hu announced the initiative behind their 0.09-micron technology, dubbed “Nexsys,” the next-generation technology for system-on-chip (SoC) semiconductor design and manufacturing by the foundry. According to a statement from TSMC, Nexsys technology consists not only of process technology, but a design environment and associated intellectual property (IP) and libraries.
TSMC expects to begin first production of Nexsys-based 0.09-micron customer devices on 8-inch wafers in the third quarter of 2002, followed by 12-inch wafers beginning in the first quarter of 2003, the statement said.
As an integral part of the speedy development of Nexsys, TSMC is offering a new “process alignment” strategy, according to an interview with Hu conducted by Silicon Strategies. TSMC and customers will coordinate the development and introduction of its 0.09-micron technology, Hu said, with TSMC and its key customers not exchanging or giving away their chip-manufacturing secrets, but forming a consensus on common design rules, electrical parameters and transistor characteristics.
Another announcement came in TSMC’s offer of a system on insulator (SOI) process at the 0.09-micron node, utilizing new technologies born from low-k materials. This comes days after an announcement of new cooperation between IBM, Sony, Sony Computer Entertainment (SCE) and Toshiba in embracing the low-resistance format for consumer electronics ICs, and a 0.065-micron low-k tool being unveiled for shipments to unnamed Japanese and US firms by Dielectric Systems.
But problems continue to be reported on the newer technology. According to sources quoted by Silicon Strategies, “TSMC is currently shipping 0.13-micron parts based on low-k, but the yields are low and the technology is more difficult than the company had originally expected.”
Also unveiled was a strategy for communications chips silicon germanium (SiGe), mixed-signal and related process technologies licensed from Conexant Systems paring down from the current 0.35-micron process to 0.18 by year’s end, then 0.09 in 2003.
According to TSMC, SiGe components for use in wireless LANs, mobile phones and other products have been delivered to customers.
TSMC’s US Technology Symposium continues on April 11 in Austin, Texas; April 16 in Boston, Massachusetts; and April 18 in Orange County, California.
